2009 fairchild semiconductor corporation FDMA1029PZ dual p-channel powertrench mosfet general description this device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra-portable applications. it features two independent p-channel mosfets with low on-state resistance for minimum conduction losses. when connected in the typical common source configuration, bi-directional current flow is possible. the microfet 2x2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. features C3.1 a, C20v. r ds(on) = 95 m @ v gs = C4.5v r ds(on) = 141 m @ v gs = C2.5v low profile C 0.8 mm maximum C in the new package microfet 2x2 mm rohs compliant 3 2 1 4 5 6 absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v ds drain-source voltage C20 v v gs gate-source voltage 12 v drain current C continuous (note 1a) C3.1 i d C pulsed C6 a power dissipation for single operation (note 1a) 1.4 p d (note 1b) 0.7 w t j , t stg operating and storage junction temperature range C55 to +150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 86 (single operation) r ja thermal resistance, junction-to-ambient (note 1b) 173 (single operation) r ja thermal resistance, junction-to-ambient (note 1c) 69 (dual operation) r ja thermal resistance, junction-to-ambient (note 1d) 151 (dual operation) c/w package marking and ordering information device marking device reel size tape width quantity 029 FDMA1029PZ 7 8mm 3000 units FDMA1029PZ dual p-channel powertrench mosfet microfet 2x2 s1 g1 d1 s2 g2 d2 pin 1 s1 g1 d2 d1 g2 s2 d1 d2 tm hbm esd protection level > 2.5kv (note 3) tm may 2009 free from halogenated compounds and antimony oxides FDMA1029PZ rev.b3(w)
electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drainCsource breakdown voltage v gs = 0 v, i d = C250 a C20 v bv dss
t j breakdown voltage temperature coefficient i d = C250 a, referenced to 25 c C12 mv/ c i dss zero gate voltage drain current v ds = C16 v, v gs = 0 v C1 a i gss gateCbody leakage v gs = 12 v, v ds = 0 v 10 a on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = C250 a C0.6 C1.0 C1.5 v v gs(th)
t j gate threshold voltage temperature coefficient i d = C250 a, referenced to 25 c 4 mv/ c r ds(on) static drainCsource onCresistance v gs = C4.5 v, i d = C3.1 a v gs = C2.5 v, i d = C2.5 a v gs = C4.5 v, i d = C3.1 a, t j =125 c 60 88 87 95 141 140 m g fs forward transconductance v ds = C10 v, i d = C3.1 a C11 s dynamic characteristics c iss input capacitance 540 pf c oss output capacitance 120 pf c rss reverse transfer capacitance v ds = C10 v, v gs = 0 v, f = 1.0 mhz 100 pf switching characteristics (note 2) t d(on) turnCon delay time 13 24 ns t r turnCon rise time 11 20 ns t d(off) turnCoff delay time 37 59 ns t f turnCoff fall time v dd = C10 v, i d = C1 a, v gs = C4.5 v, r gen = 6 36 58 ns q g total gate charge 7.0 10 nc q gs gateCsource charge 1.1 nc q gd gateCdrain charge v ds = C10 v, i d = C3.1 a, v gs = C4.5 v 2.4 nc FDMA1029PZ dual p-channel powertrench mosfet drainCsource diode characteristics and maximum ratings i s maximum continuous sourceCdrain diode forward current -1.1 a v sd sourceCdrain diode forward voltage v gs = 0 v, i s = C1.1 a (note 2) C0.8 C1.2 v t rr diode reverse recovery time 25 ns q rr diode reverse recovery charge i f = C3.1 a, di f /dt = 100 a/s 9 nc FDMA1029PZ rev.b3(w)
notes: 1. r ja is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ja is determined by the user's board design. (a) r ja = 86 c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick pcb. for single operation. (b) r ja = 173 c/w when mounted on a minimum pad of 2 oz copper. for single operation. (c) r ja = 69 o c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 ? x 1.5 ? x 0.062 ? thick pcb. for dual operation. (d) r ja = 151 o c/w when mounted on a minimum pad of 2 oz copper. for dual operation. 2. pulse test : pulse width < 300 us, duty cycle < 2.0% 3. the diode connected between the gate and source serves only as protection against esd. no gate overvoltage rating is implied . a)86 o c/w when mounted on a 1 in 2 pad of 2 oz copper. b)173 o c/w when mounted on a minimum pad of 2 oz copper. c)69 o c/w when mounted on a 1 in 2 pad of 2 oz copper. d)151 o c/w when mounted on a minimum pad of 2 oz copper. FDMA1029PZ rev.b3(w)
typical characteristics 0 1 2 3 4 5 6 0 0.4 0.8 1.2 1.6 2 -v ds , drain-source voltage (v) -i d , drain current (a) 3.0v 2.5v 3.5v v gs = 45v 2.0v 1.5v 0.6 1 1.4 1.8 2.2 2.6 0123456 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = -2.0v -3.5v -4.5v -3.0v -2.5v -4.0v figure 1. on-region characteristics. figur e 2. on-resistance variation with drain current and gate voltage. 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = -3.1a v gs = -4.5v 0.04 0.08 0.12 0.16 0.2 0246810 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = -1.55a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 1 2 3 4 5 6 00.511.522.5 -v gs , gate to source voltage (v) -i d , drain current (a) t a = 125 o c 25 o c -55 o c v ds = -5v 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -v sd , body diode forward voltage (v) -i s , reverse drain current (a) t a = 125 o c 25 o c -55 o c v gs = 0v figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. FDMA1029PZ dual p-channel powertrench mosfet FDMA1029PZ rev.b3(w)
typical characteristics 0 2 4 6 8 10 0 2 4 6 8 101214 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -3.1a v ds = -5v -15v -10v 0 200 400 600 800 1000 0 4 8 12 16 20 -v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v figure 7. gate charge characteri stics. figure 8. capacitance characteristics. 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-source voltage (v) -i d , drain current (a) dc 10s 1s 100ms r ds(on) limit v gs = -4.5v single pulse r ja = 173 o c/w t a = 25 o c 10ms 1ms 100us 0 10 20 30 40 50 0.0001 0.001 0.01 0.1 1 10 100 1000 p(pk), peak transient power (w) single pulse r ja = 173c/w t a = 25c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transient thermal resistance r ja (t) = r(t) * r ja r ja =173 c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p(pk) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1b. transient thermal response will change depending on the circuit board design. FDMA1029PZ dual p-channel powertrench mosfet FDMA1029PZ rev.b3(w)
rev3 dimensional outline and pad layout ` FDMA1029PZ dual p-channel powertrench mosfet FDMA1029PZ rev.b3(w)
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